Xilinx and Micron Demonstrate First Hardware Interoperability of FPGA and RLDRAM 3 Memory Interface Standard (Xilinx, Inc. 38076) March 13, 2012 -- Xilinx, Inc. and Micron Technology, Inc. today announced the first public hardware demonstration of an FPGA interfacing with RLDRAM 3 memory, a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables.
Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1600Mbps, Micron's high-performance RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60% higher data rate and memory bandwidth compared to that of the previous generation (Virtex-6 FPGAs/ RLDRAM2 memory standard). RLDRAM 3 memory enables 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency. Hardware demonstrations of the Xilinx RLDRAM 3 Memory interface IP core are available now with user configurable IP cores available in ISE Design Suite 13.4 in September 2012.
Rfdesignline. Xilinx and Micron demo interoperability of FPGA and RLDRAM 3 memory interface standard - 2012-03-13 18:42:12. Xilinx and Micron make RLDRAM 3 memory interface work - 3/14. Xilinx and Micron Technology have demonstrated an FPGA interfacing with RLDRAM 3 memory, an emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables.
Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1,600Mbit/s, Micron’s RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60 percent higher data rate and memory bandwidth compared to that of the previous generation Virtex-6 FPGAs/RLDRAM2 memory standard. RLDRAM 3 memory enables 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency. “Xilinx has been a longtime partner of Micron, going back to the early definition efforts of RLDRAM 3 memory,” said Robert Feurle, v-p of Micron’s DRAM marketing. Virtex-7 and Kintex-7 FPGAs are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3.
Related posts. Xilinx, Micron platform enables higher data rates for 40/100G networking systems. 14 March 2012.
Micron shows off the first working RLDRAM 3 hardware - Xilinx collaboration bears fruit. Top American memory maker Micron and FPGA maestro Xilinx have publicly demoed the first working RLDRAM 3 and memory controller setup, allowing logic-board manufacturers to begin implementing the memory standard.
The demo involved a Xilinx Virtex 7 FPGA interfacing with Micron’s RLDRAM 3 module array. The test system delivered 60 percent higher throughput on networking applications - over previous generation tech - and operates at speeds of up to 800 MHz (1.6 Mbps). It also offers a lower power envelope and more flexible memory configurations. Micron developed RLDRAM together with the now-defunct memory division of Infineon, almost 13 years ago. Its main purpose was to create a memory with faster response times in random access, something standard DRAM has evolved very little over the course of the years. RLDRAM 3 is expertly positioned into the whole ‘caching’ business, which allows for all sorts of performance enhancements in just about any processing background. Micron, Xilinx Demonstrate Working RLDRAM 3 Prototypes. Micron Technology and Xilinx this week demonstrated an FPGA interfacing with RLDRAM 3 [reduced latency DRAM] memory, a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables.
Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1600MHz, Micron's high-performance RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60% percent higher data rate and memory bandwidth compared to that of the previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard). RLDRAM 3 memory uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios. Micron and Xilinx show off RLDRAM 3.